FIG. 4 shows a first example of prior art signal output circuits. In this circuit, a signal IN inputted through an input terminal 3 is inverted by an inverter 1, and then outputted through an output terminal 4 as a signal /.phi. opposite in phase to the input signal IN. Further, the signal inverted by the inverter 1 is further inverted by another inverter 2, and then outputted through another output terminal 5 as a signal .phi. in phase with the input signal IN.
The operation of the circuit shown in FIG. 4 will be described hereinbelow.
The signal inputted through the input terminal 3 is inverted by the inverter 1, and then outputted through the output terminal 4 as an opposite-phase signal /.phi. with respect to the input signal IN. On the other hand, the signal inputted through the input terminal 3 is inverted by the inverter 1 and further by the inverter 2, and then outputted through the output terminal 5 as an opposite-phase signal .phi. with respect to the signal /.phi. outputted through the output terminal 4.
Therefore, the signal /.phi. outputted through the output terminal 4 is perfectly opposite in phase to the signal .phi. outputted through the output terminal 5 from the logical standpoint. In practice, however, the mutual phase relationship between the two is not necessarily accurate due to a delay of the inverter 2.
In more detail with reference to FIG. 6, the output signal /.phi. (as shown by (B)) outputted through the output terminal 4 is delayed from the input signal IN (as shown by (A)) due to a delay time of the inverter 1. On the other hand, the output signal .phi. (as shown by (C)) outputted through the output terminal 5 is delayed from the input signal IN due to delay times of both the inverters 1 and 2.
Accordingly, when the input signal IN rises at a time t1 and falls at a time t4 as shown by (A) in FIG. 6, the signal /.phi. outputted through the output terminal 4 falls at a time t2 and rises at a time t5 due to a delay time T1 of the inverter 1 as shown by (B). On the other hand, the signal .phi. outputted through the output terminal 5 rises at a time t3 and falls at a time t6 due to an addition T2 of the two delay times of the two inverters 1 and 2 as shown by (C).
FIG. 5 shows a second example of prior art signal output circuits. In this circuit, a signal IN inputted through an input terminal 3 is given to three inverters 1, 8 and 6, respectively. The output of the inverter 6 is given to the base of an NPN transistor 9. The collector of this NPN transistor 9 is pulled up by a supply voltage Vcc, and the emitter thereof is connected to an output of an output terminal 4 together with an output of the inverter 8. On the other hand, an output of the inverter 8 is given to other two inverters 7 and 2, respectively. An output of the inverter 7 is given to the base of an NPN transistor 10. The collector of this NPN transistor 10 is pulled up by the supply voltage Vcc, and then connected to an output terminal 5 together with the output of the inverter 2.
The operation of this circuit shown in FIG. 5 will be described hereinbelow.
When the input signal IN inputted through the input terminal 3 falls from a high level to a low level, the outputs of the three inverters 1, 6 and 8 rise to the high level, respectively. Since the output of the inverter 6 in at the high level, the NPN transistor 9 is turned on, so that the output terminal of the inverter 1 (i.e., the signal /.phi. at the output terminal 4) is pulled up to the high level toward the supply voltage Vcc. In other words, when the level at the output terminal 4 is pulled up from the low level to the high level, the NPN transistor 9 serves to increase the drive capability of the circuit, that is, the circuit response speed, in particular when a heavy load is connected to the output terminal 4. On the other hand, when the input signal IN inputted through the input terminal 3 falls from the high level to the low level, the output level of the inverter 8 changes to the high level. As a result, the output levels of the two inverters 7 and 2 change to the low level. Therefore, since the output of the inverter 7 is given to the base of the NPN transistor 10, the NPN transistor 10 is turn off, so that the signal .phi. outputted through the output terminal 5 changes to the low level.
In contrast with this, when the input signal IN inputted through the input terminal 3 rises from the low level to the high level, the outputs of the three inverters 1, 6 and 8 fall to the low level, respectively. Since the output of the inverter 6 is at the low level, the NPN transistor 9 is turned off, so that the output terminal of the inverter 1 (i.e., the signal /.phi. at the output terminal 4) is disconnected from the supply voltage Vcc. On the other hand, the low-level signal /.phi. is outputted to the output terminal 4 through the inverter 1.
On the other hand, when the input signal IN inputted through the input terminal 3 rises from the low level to the high level, the output level of the inverter 8 changes to the low level. As a result, the output levels of the two inverters 7 and 2 change to the high level. Therefore, since the output of the inverter 7 is given to the base of the NPN transistor 10, the NPN transistor 10 is turned on, so that the signal .phi. outputted through the output terminal 5 is pulled up from the low level to the high level. As a result, the level of the signal .phi. outputted through the output terminal 5 changes to the high level. In this case, it is possible to increase the drive capability of the circuit, that is, to improve the circuit response speed when a heavy load is connected to the output terminal 4.
In the prior art circuit as shown in FIG. 5, however, since the number of the inverters connected between the input terminal 3 and the output terminal 4 is different from that between the input terminal 3 and the output terminal 5 in the same way as with the case of the circuit shown in FIG. 4, although the drive capability can be it proved by the presence of the two NPN transistors 9 and 10, since there exists basically a difference in delay time between the two routes, it is impossible to obtain the accurate opposite-phase relationship between the signal /.phi. outputted through the terminal 4 and that .phi. outputted through the terminal 5.
FIG. 7 shows a third example of prior art signal output circuits. In this circuit, an enable signal /EN inputted through an input terminal 3 is inverted by an inverter 1, and then given to two NAND circuits 11 and 12 and an inverter 2. An output of the inverter 2 is given to two NOR circuits 13 and 14 via an output terminal 5. On the other hand, a data signal D-In inputted through an input terminal 44 is given to a NAND circuit 11. An output of the NAND circuit 11 is given to a NOR circuit 13 and an inverter 15. An output of the inverter 15 is given to a NOR circuit 14. An output of the NOR circuit 13 is given to the base of an NPN transistor 22. The collector of the transistor 22 is pulled up by a supply voltage Vcc, and the emitter thereof is connected to the base of a transistor 23. The collector of the transistor 23 is pulled up by the supply voltage Vcc, and the emitter thereof is connected to an output terminal 45. The output of the NOR circuit 14 is applied to the gate of an NMOS transistor 17, and the output of the NAND circuit 12 is applied to the gate of an NMOS transistor 16. The drain of the MOS transistor 17 is pulled up by the supply voltage Vcc via a resistor 21. Further, the source of the MOS transistor 17 is connected to the drain of the MOS transistor 16, and the source of the MOS transistor 16 is connected to ground GND. The drain of the MOS transistor 17 is connected to the emitter of the transistor 22 via a Zener diode 19 and similarly to the emitter of the transistor 23 via another Zener diode 18. Further, a resistor 20 is connected between the emitters of the two transistors 22 and 23. Further, a junction point between the source of the MOS transistor 17 and the drain of the MOS transistor 16 is connected to the base of an NPN transistor 24. The emitter of the transistor 24 is connected to the ground GND, and the emitter of the transistor 23 is connected to an output terminal 45 through which a signal Q is outputted.
The operation of the circuit shown in FIG. 7 will be described hereinbelow.
The circuit shown in FIG. 7 constructs a buffer circuit provided with three-state functions. On the basis of the signal /EN inputted through the input terminal 3 and the signal D-IN inputted through the input terminal 44, the level of the output terminal 45 can be controlled to one of three levels (a low level, a high level, and a high inpedance).
Here, if the data D-IN inputted through the input terminal 44 is at the low level, the output of the NAND circuit 11 is at the high level, so that the output of the NCR circuit 13 is at the low level and the output of the inverter 15 is at the low level. In other words, the NOR circuit 14 and the NAND circuit 12 function as an inverter for an input signal inputted through the other input terminal.
Under these conditions, since the base of the transistor 22 is at the low level, the transistor 22 is turned off, so that the transistor 23 is also turned off.
Under these conditions, when the signal /EN inputted through the input terminal 3 is at the low level, since the output of the inverter 1 is at the high level, the output of the inverter 2 is at the low level.
As a result, the output of the NAND circuit 12 is at the low level. Since this low-level signal is applied to the gate of the MOS transistor 16, the transistor 16 is turned off.
On the other hand, the output of the NOR circuit 14 changes to the high level, so that the MOS transistor 17 is turned on in response to this high-level signal. As a result, a base current is supplied from the supply voltage Vcc to the base of the transistor 24 through a resistor 21 to turn on the transistor 24, so that the low-level signal is outputted through the output terminal 45.
On the other hand, when the signal /EN inputted to the input terminal 2 is at the high level, the output of the inverter 1 is at the low level and that of the inverter 2 is at the high level.
As a result, the output of the NAND circuit 12 is at the high level, so that the MOS transistor 16 is turned on in response to this high-level signal.
On the other hand, the output of the NOR circuit 14 is at the low level, so that the MOS transistor 17 is turned off in response to this low-level signal.
As a result, since the base of the transistor 24 is connected to the ground GND through the MOS transistor 16, the transistor 24 is turned off. On the other hand, since the transistor 23 is turned off, the output terminal 45 changes to a high impedance output state.
In contrast with this, when the data D-IN inputted through the input terminal 44 is at the high level, the NAND circuit 11 functions as an inverter for a signal inputted to the other input terminal thereof.
Under these conditions, when the signal /EN inputted through the input terminal 3 is at the low level, the output of the inverter 1 is at the high level; the output of the NAND circuit 11 is at the low level; and the output of the inverter 15 is at the high level. That is, the output of the NOR circuit 14 changes to the low level, so that the output of the NAND circuit 12 changes to the high level.
As a result, the gate of the MOS transistor 17 is at the low level, and the gate of the MOS transistor 16 is at the high level. As a result, the MOS transistor 17 is turned off, and the MOS transistor 16 is turned on, so that the base of the transistor 24 is connected to the ground GND; that is, the transistor 24 is turned off.
On the other hand, since the output of the inverter 2 is at the low level, the output of the NOR circuit 13 is at the high level.
Under these conditions, since the base of the transistor 22 is at the high level, the transistor 22 is turned on, so that a base current is supplied from the supply voltage Vcc to the base of the transistor 23 through the emitter of the transistor 22. As a result, a high-level signal Q is outputted through the output terminal 45.
On the other hand, under these conditions, when the signal /EN inputted through the input terminal 3 changes to the high level, since the output of the inverter 1 changes to the low level, the outputs of the inverter 2 and the NAND circuit 11 are both at the high level. As a result, the output of the NOR circuit 13 is at the low level; the output of the inverter 15 is at the low level; the output of the NOR circuit 14 is at the low level; and the output of the NAND circuit 12 is at the high level.
Under these conditions, since the output of the NOR circuit 13 is at the low level, the transistor 22 is turned off. Therefore, the transistor 23 whose base is connected to the emitter of the transistor 22 is also turned off.
On the other hand, the gate of the MOS transistor 17 is at the low level, and the gate of the MOS transistor 16 is at the high level. As a result, the MOS transistor 17 is turned off; the MOS transistor 16 is turned on; and the base of the transistor 24 is connected to the ground GND. Therefore, the transistor 24 is turned off.
As a result, the two transistors 23 and 24 are both turned off, so that the output terminal 45 is kept at a high impedance state.
In other words, the output state of the output terminal 45 can be controlled into three states on the basis of the level of the input signal /EN at the input terminal 3 and the levels of the two-phase signals of the input signal D-IN at the input terminal 44. Here, the circuit operation is taken into account by designating the output signals of the two inverters 1 and 2 as /.phi. and .phi., respectively as shown in FIG. 7.
In this case, when the three-state control is constructed by logic on the basis of internal two-phase signals of/.phi. and .phi., the response speed of the circuit is inevitably decided on the basis of the level change of a more delayed signal of the two signals/.phi. and .phi., that is, the change of the signal .phi. in phase with the signal /EN.
In more practice, when the signal /EN changes from the high level to the low level and the signal /.phi. changes to the high level, the two NAND circuits 11 and 12 change from the disable state to the enable state. However, in order to output the high or low level through the output terminal 45, the two NOR circuits 13 and 14 must output a normal signal, respectively.
Therefore, it is to be understood that the response speed of the circuit as shown in FIG. 7 depends upon the delay time between the signal /EN inputted through the input terminal 3 and the signal .phi. obtained through the two inverters 1 and 2. In other words, in the case of the control on the basis of one-phase input inversion signal of the signal /EN, the delay time can be minimized. In the case of logic on the basis of the one-phase input in-phase signal control or two-phase signal control, however, since the response speed is dependent upon that of the more delayed signal, the response speed of the circuit is inevitably reduced.
In the prior art signal output circuits constructed as described above, where two-phase signals are generated in response to one-phase signal and the generated signals are applied to a latch circuit, a flip-flop circuit, a three-state logic circuit, etc., since these circuits are basically provided with the alternating characteristics, there inevitably exists an imbalance in delay time in the internal circuits, so that it is difficult to keep constant the phase relationship between the generated two-phase signals stably. In particular, when these two-phase signals are used as clocks, this causes an erroneous operation of the circuit, thus resulting in a serious problem. In particular, when the operation speed of the circuit increases, there exists such a possibility that the two-phase signals become in phase with respect to each other in an extreme case. Therefore, when these signals are used as clock signals, a problem arises in that an erroneous operation such as hazard, the absence of data, etc. occurs. These problems may be overcome by positively delaying the leading signal so that the phase thereof can match that of the more delayed signal. However, this method is not preferable when a high operation speed is required for the output circuit. Accordingly, an effective method of operating the output circuit on the basis of multi-phase clocks has been so far required.